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october 2008 rev 8 1/33 1 vnh2sp30-e automotive fully integrated h-bridge motor driver features 5v logic level compatible inputs undervoltage and overvoltage shut-down overvoltage clamp thermal shut down cross-conduction protection linear current limiter very low stand-by power consumption pwm operation up to 20 khz protection against loss of ground and loss of v cc current sense output proportional to motor current package: ecopack ? description the vnh2sp30-e is a full bridge motor driver intended for a wide range of automotive applications. the device incorporates a dual monolithic high side driver and two low side switches. the high side driver switch is designed using stmicroelectronic?s well known and proven proprietary vipower ? m0 technology which permits efficient integration on the same die of a true power mosfet with an intelligent signal/protection circuitry. the low side switches are vertical mosfets manufactured using stmicroelectronic?s proprietary ehd (?stripfet??) process. the three die are assembled in the multipowerso-30 package on electrically isolated leadframes. this package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. moreover, its fully symmet rical mechanical design allows superior manufact urability at board level. the input signals in a and in b can directly interface to the microcontroller to select the motor direction and the brake condition. the diag a /en a or diag b /en b , when connected to an external pull-up resistor, enable one leg of the bridge. they also provide a feedback digital diagnostic signal. the normal condition operation is explained in table 12: truth table in normal operating conditions on page 14 . the motor current can be monitored with the cs pin by delivering a current proportional to its value. the speed of the motor can be controlled in all possible conditions by the pwm up to 20 khz. in all cases, a low level state on the pwm pin will turn off both the ls a and ls b switches. when pwm rises to a high level, ls a or ls b turn on again depending on the input pin state. type r ds(on) i out v ccmax vnh2sp30-e 19m max ( per leg) 30a 41v multipowerso-30 ? table 1. device summary package order codes tube tape and reel multipowerso-30 vnh2sp30-e VNH2SP30TR-E www.st.com
contents vnh2sp30-e 2/33 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 powersso-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 thermal calculation in clockwise and anti-clockwise operation in steady- state mode 26 4.1.2 thermal resistances definition (values according to the pcb heatsink area) 26 4.1.3 thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.4 single pulse thermal impedance definition (values according to the pcb heatsink area) . . . . . . . . . . . . . . . . . . . . . 26 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 ecopack? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 multipowerso-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
vnh2sp30-e list of tables 3/33 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. logic inputs (ina, inb, ena, enb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. switching (v cc =13v, r load = 0.87w , unless otherwise specified) . . . . . . . . . . . . . . . . 10 table 10. protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 11. current sense (9v < v cc < 16v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 12. truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 table 13. truth table in fault conditions (detected on outa). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 14. electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 15. thermal calculation in clockwise and anti -clockwise operation in steady-state mode . . . . 26 table 16. thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. multipowerso-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of figures vnh2sp30-e 4/33 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. definition of the low side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. definition of the high side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. definition of dynamic cross conduction current during a pwm operation. . . . . . . . . . . . . . 13 figure 8. on state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. high level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. high level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 19. low level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 20. pwm high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. pwm low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. pwm high level current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 24. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 26. on state high side resistance vs tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. on state low side resistance vs tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 28. turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29. turn-off delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 30. output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 31. output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 32. typical application circuit for dc to 20 kh z pwm operation short circuit protection . . . . . 20 figure 33. behavior in fault condition (how a fault can be cleared). . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 34. half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 35. multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 36. waveforms in full bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 37. waveforms in full bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 38. multipowerso-30? pc board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 39. chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 40. auto and mutual rthj-amb vs pcb copper area in open box free air condition . . . . . . . . . 25 figure 41. multipowerso-30 hsd thermal impedance junction ambient single pulse . . . . . . . . . . . . 27 figure 42. multipowerso-30 lsd thermal impedance junction ambient single pulse . . . . . . . . . . . . . 27 figure 43. thermal fitting model of an h-bridge in multipowerso-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 44. multipowerso-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 45. multipowerso-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 46. multipowerso-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 47. multipowerso-30 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
vnh2sp30-e block diagram and pin description 5/33 1 block diagram and pin description figure 1. block diagram table 2. block description name description logic control allows the turn-on and the turn-off of the high side and the low side switches according to the truth table overvoltage + undervoltage shuts down the device outside the range [5.5v..16v] for the battery voltage high side and low side clamp voltage protects the high side and the low side switches from the high voltage on the battery line in all configurations for the motor high side and low side driver drives the gate of the concerned switch to allow a proper r ds(on) for the leg of the bridge linear current limiter limits the motor current by reducing the high side switch gate-source voltage when short-circuit to ground occurs overtemperature protection in case of short-circuit with the increase of the junction?s temperature, shuts down the concerned high side to prevent its degradation and to protect the die fault detection signals an abnormal behavior of the switches in the half-bridge a or b by pulling low the concerned en x /diag x pin logic v cc out a diag a /en a in b in a gnd a cs diag b /en b ls a clamp hs a ls a hs a overtemperature a overtemperature b o v + u v current limitation a out b gnd b ls b hs b current limitation b driver hs a driver ls b driver hs b driver clamp hs b clamp ls b clamp ls a pwm 1/k 1/k
block diagram and pin description vnh2sp30-e 6/33 figure 2. configuration diagram (top view) table 3. pin definitions and functions pin no symbol function 1, 25, 30 out a , heat slug3 source of high side switch a / drain of low side switch a 2, 4, 7, 12, 14, 17, 22, 24, 29 nc not connected 3, 13, 23 v cc , heat slug1 drain of high side switches and power supply voltage 6en a /diag a status of high side and low side switches a; open drain output 5in a clockwise input 8 pwm pwm input 9 cs output of current sense 11 in b counter clockwise input 10 en b /diag b status of high side and low side switches b; open drain output 15, 16, 21 out b , heat slug2 source of high side switch b / drain of low side switch b 26, 27, 28 gnd a source of low side switch a (1) 1. gnd a and gnd b must be externally connected together. 18, 19, 20 gnd b source of low side switch b (1) out a out a out a out b out b nc v cc nc in a en a /diag a nc pwm cs en b /diag b in b nc nc v cc out b nc nc gnd a gnd a gnd a nc v cc nc gnd b gnd b gnd b 1 15 16 30 v cc heat slug1 out b heat slug2 out a heat slug3
vnh2sp30-e block diagram and pin description 7/33 table 4. pin functions description name description v cc battery connection gnd a , gnd b power grounds; must always be externally connected together out a , out b power connections to the motor in a , in b voltage controlled input pins with hyster esis, cmos compatible. these two pins control the state of the bridge in normal operation according to the truth table (brake to v cc , brake to gnd, clockwise and counterclockwise). pwm voltage controlled input pin with hysteresis, cmos compatible. gates of low side fets are modulated by the pwm signal during their on phase allowing speed control of the motor. en a /diag a , en b /diag b open drain bidirectional logic pins. these pins must be connected to an external pull up resistor. when externally pulled low, they disable half-bridge a or b. in case of fault detection (thermal shutdown of a high side fet or excessive on state voltage drop across a low side fet), these pins are pulled low by the device (see truth table in fault condition). cs analog current sense output. this output sources a current proportional to the motor current. the information can be read back as an analog voltage across an external resistor.
electrical specifications vnh2sp30-e 8/33 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings v cc in a gnd b i s i outa i ina v ina v cc v outa i sense v outb diag a /en a i ena i gnd i outb in b i inb diag b /en b i enb v enb v ena v inb v sense out a out b pwm cs i pw v pw gnd a gnd table 5. absolute maximum ratings symbol parameter value unit v cc supply voltage +41 v i max maximum output current (continuous) 30 a i r reverse output current (continuous) -30 i in input current (in a and in b pins) 10 ma i en enable input current (diag a /en a and diag b /en b pins) 10 i pw pwm input current 10 v cs current sense maximum voltage -3/+15 v v esd electrostatic discharge (r = 1.5k , c = 100pf) ?cs pin ? logic pins ? output pins: out a , out b , v cc 2 4 5 kv kv kv t j junction operating temperature internally limited c t c case operating temperature -40 to 150 t stg storage temperature -55 to 150
vnh2sp30-e electrical specifications 9/33 2.2 electrical characteristics v cc = 9v up to 16 v; -40c < t j < 150c, unless otherwise specified. table 6. power section symbol parameter test cond itions min typ max unit v cc operating supply voltage 5.5 16 v i s supply current off state with all fault cleared & enx=0 in a =in b =pwm=0; t j = 25c; v cc =13v in a =in b =pwm=0 off state: in a =in b =pwm=0 12 2 30 60 a a ma on state: in a or in b =5v, no pwm 10 ma r onhs static high side resistance i out = 15a; t j = 25c 14 m i out = 15a; t j = -40 to 150c 28 r onls static low side resistance i out = 15a; t j = 25c 5 i out = 15a; t j = -40 to 150c 10 v f high side free- wheeling diode forward voltage i f = 15a 0.8 1.1 v i l(off) high side off state output current (per channel) t j =25c; v outx =en x =0v; v cc =13v 3 a t j = 125c; v outx =en x =0v; v cc =13v 5 i rm dynamic cross- conduction current i out = 15a (see figure 7 )0.7a table 7. logic inputs (in a , in b , en a , en b ) symbol parameter test cond itions min typ max unit v il input low level voltage normal operation (diag x /en x pin acts as an input pin) 1.25 v v ih input high level voltage 3.25 v ihyst input hysteresis voltage 0.5 v icl input clamp voltage i in =1ma 5.5 6.3 7.5 i in = -1ma -1.0 -0.7 -0.3 i inl input low current v in =1.25v 1 a i inh input high current v in =3.25v 10 v diag enable output low level voltage fault operation (diag x /en x pin acts as an output pin); i en =1ma 0.4 v
electrical specifications vnh2sp30-e 10/33 table 8. pwm symbol parameter test co nditions min typ max unit v pwl pwm low level voltage 1.25 v i pwl pwm pin current v pw = 1.25v 1 a v pwh pwm high level voltage 3.25 v i pwh pwm pin current v pw = 3.25v 10 a v pwhhyst pwm hysteresis voltage 0.5 v v pwcl pwm clamp voltage i pw = 1ma v cc +0.3 v cc +0.7 v cc +1.0 i pw = -1ma -6.0 -4.5 -3.0 c inpwm pwm pin input capacitance v in =2.5v 25 pf table 9. switching (v cc =13v, r load =0.87 , unless otherwise specified) symbol parameter test co nditions min typ max unit f pwm frequency 0 20 khz t d(on) turn-on delay time input rise time < 1s (see figure 6 ) 250 s t d(off) turn-off delay time input rise time < 1s (see figure 6 ) 250 t r rise time (see figure 5 )11.6 t f fall time (see figure 5 )1.22.4 t del delay time during change of operating mode (see figure 4 ) 300 600 1800 t rr high side free wheeling diode reverse recovery time (see figure 7 )110ns t off(min) (1) 1. to avoid false short to battery detection during pwm operation, the pwm signal must be low for a time longer than 6s. pwm minimum off time 9v < v cc <16v; t j = 25c; l = 250h; i out = 15a 6s table 10. protection and diagnostic symbol parameter test co nditions min typ max unit v usd undervoltage shut-down 5.5 v undervoltage reset 4.7 v ov overvoltage shut-down 16 19 22 i lim high side current limitation 30 50 70 a v clp total clamp voltage (v cc to gnd) i out = 15a 43 48 54 v t tsd thermal shut-down temperature v in = 3.25v 150 175 200 c t tr thermal reset temperature 135 t hyst thermal hysteresis 7 15
vnh2sp30-e electrical specifications 11/33 figure 4. definition of the delay times measurement table 11. current sense (9v < v cc <16v) symbol parameter test conditions min typ max unit k 1 i out /i sense i out = 30a; r sense =1.5k ; t j = -40 to 150c 9665 11370 13075 k 2 i out /i sense i out =8a; r sense =1.5k ; t j = -40 to 150c 9096 11370 13644 dk 1 /k 1 (1) 1. analog sense current drift is deviation of fact or k for a given device over (-40c to 150c and 9v < v cc < 16v) with respect to its value measured at t j = 25c, v cc =13v. analog sense current drift i out = 30a; r sense =1.5k ; t j = -40 to 150c -8 +8 % dk 2 /k 2 (1) analog sense current drift i out >8a; r sense =1.5k ; t j = -40 to 150c -10 +10 i senseo analog sense leakage current i out =0a; v sense =0v; t j = -40 to 150c 065a t t v inb v ina t pwm t i load t del t del
electrical specifications vnh2sp30-e 12/33 figure 5. definition of the low side switching times figure 6. definition of the high side switching times t f pwm t t v outa, b 20% 90% 80% 10% t r t t v outa v ina 90% 10% t d(on) t d(off)
vnh2sp30-e electrical specifications 13/33 figure 7. definition of dynamic cross conduction current during a pwm operation t t i motor pwm t v outb t i cc t rr i rm in a =1, in b =0
electrical specifications vnh2sp30-e 14/33 note: notice that saturation detection on the low side power mosfet is possible only if the impedance of the short-circuit from the output to the battery is less than 100m when the device is supplied with a battery voltage of 13.5v. table 12. truth table in normal operating conditions in a in b diag a /en a diag b /en b out a out b cs operating mode 1 1 11 h h high imp. brake to v cc 0l i sense =i out /k clockwise (cw) 0 1 l h counterclockwise (ccw) 0 l high imp. brake to gnd table 13. truth table in fault conditions (detected on out a ) in a in b diag a /en a diag b /en b out a out b cs 1 1 0 1 open h high imp. 0l 0 1hi outb /k 0l high imp. x x 0 open 1 1 hi outb /k 0 l high imp. fault information protection action
vnh2sp30-e electrical specifications 15/33 table 14. electrical transient requirements iso t/r - 7637/1 test pulse test level i test level ii test level iii test level iv test levels delays and impedance 1 -25v -50v -75v -100v 2ms, 10 2 +25v +50v +75v +100v 0.2ms, 10 3a -25v -50v -100v -150v 0.1s, 50 3b +25v +50v +75v +100v 4 -4v -5v -6v -7v 100ms, 0.01 5 +26.5v +46.5v +66.5v +86.5v 400ms, 2 iso t/r - 7637/1 test pulse test levels result i test levels result ii test levels result iii test levels result iv 1 c ccc 2 3a 3b 4 5 (1) 1. for load dump exceeding the above value a centralized suppressor must be adopted. eee class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
electrical specifications vnh2sp30-e 16/33 2.3 electrical characteristics curves figure 8. on state supply current figure 9. off state supply current -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 is (ma) vcc=13v ina or inb=5v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 5 10 15 20 25 30 35 40 45 50 is (a) vcc=13v figure 10. high level input current figure 11. input clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iinh (a) vin=3.25v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 vicl (v) iin =1ma figure 12. input high level voltage figure 13. input low level voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 vil (v)
vnh2sp30-e electrical specifications 17/33 figure 14. input hysteresis voltage figure 15. high level enable pin current -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 vihyst (v) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 ienh (a) ven=3.25v figure 16. delay time during change of operation mode figure 17. enable clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 100 200 300 400 500 600 700 800 900 1000 tdel (s) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 vencl (v) ien=-1ma figure 18. high level enable voltage figure 19. low level enable voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 venh (v) vcc=9v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 venl (v) vcc=9v
electrical specifications vnh2sp30-e 18/33 figure 20. pwm high level voltage figure 21. pwm low level voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 vpwh (v) vcc=9v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 vpwl (v) vcc=9v figure 22. pwm high level current figure 23. overvoltage shutdown -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 ipwh (a) vcc=9v vpw=3.25v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 10 12.5 15 17.5 20 22.5 25 27.5 30 vov (v) figure 24. undervoltage shutdown figure 25. current limitation -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vusd(v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 30 35 40 45 50 55 60 65 70 75 80 ilim (a)
vnh2sp30-e electrical specifications 19/33 figure 26. on state high side resistance vs t case figure 27. on state low side resistance vs t case -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 5 10 15 20 25 30 35 40 ronhs (mohm) vcc=9v; 16v iout=15a -50 -25 0 25 50 75 100 125 150 175 tc (c) 0 1 2 3 4 5 6 7 8 9 ronls (mohm) vcc=9v; 16v iout=15a figure 28. turn-on delay time figure 29. turn-off delay time -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 60 80 100 120 140 160 180 200 220 240 260 td(on) (s) -50 -25 0 25 50 75 100 125 150 175 tc (c) 100 110 120 130 140 150 160 170 180 190 200 td(off) (s) figure 30. output voltage rise time figure 31. output voltage fall time -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 tr (s) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 tf (s)
application information vnh2sp30-e 20/33 3 application information in normal operating conditions the diag x /en x pin is considered as an input pin by the device. this pin must be externally pulled high. pwm pin usage: in all cases, a ?0? on the pwm pin will turn off both ls a and ls b switches. when pwm rises back to ?1?, ls a or ls b turn on again depending on the input pin state. figure 32. typical application circuit for dc to 20 khz pwm operation short circuit protection note: the value of the blocking capacitor (c) depends on the applicat ion conditions and defines voltage and current ripple onto suppl y line at pwm operation. stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goe s into tri-state. this causes a hazardous overvolt age if the capacitor is not big enough. as basic orientation, 500f per 10a load cur rent is recommended. in case of a fault condition the diag x /en x pin is considered as an output pin by the device.the fault conditions are: overtemperature on one or both high sides short to battery condition on the output (saturation detection on the low side power mosfet) possible origins of fault conditions may be: out a is shorted to ground overtemperature detection on high side a. out a is shorted to v cc low side power mosfet saturation detection. m c reg 5v + 5v hs a hs b ls a ls b v cc diag a /en a cs in a pwm out a out b d s g b) n mosfet 3.3k 1k 1k 1k 10k 33nf 1.5k v cc 100k diag b /en b +5v 1k 3.3k in b 1k gnd a gnd b c
vnh2sp30-e application information 21/33 when a fault condition is detected, the user can know which power element is in fault by monitoring the in a , in b , diag a /en a and diag b /en b pins. in any case, when a fault is detected, the faulty leg of the bridge is latched off. to turn on the respective output (out x ) again, the input signal must rise from low to high level. note: in case of the fault condition is not removed, the procedure for unlatching and sending the device in stby mode is: - clear the fault in the device (toggle : ina if ena=0 or inb if enb=0) - pull low all inputs, pwm and diag/en pins within tdel. if the diag/en pins are already low, pwm=0, the fault can be cleared simply toggling the input. the device will enter in stby mode as soon as the fault is cleared. 3.1 reverse battery protection three possible solutions can be considered: 1. a schottky diode d connected to v cc pin 2. an n-channel mosfet connected to the gnd pin (see figure 32: typical application circuit for dc to 20 khz pwm operation short circuit protection on page 20 ) 3. a p-channel mosfet connected to the v cc pin the device sustains no more than -30a in reverse battery conditions because of the two body diodes of the power mosfets. additionally, in reverse battery condition the i/os of vnh2sp30-e are pulled down to the v cc line (approximately -1.5v) . a series resistor must figure 33. behavior in fault condition (how a fault can be cleared) in a in b diag a en a diag b en b iout a ? out b fault a (internal signal) fault b (internal signal) normal operation out b shorted to v cc t del fault cleared stby (*) normal operation out b shorted to gnd t del fault cleared normal operation device latched device latched device unlatched in a in b diag a en a diag b en b iout a ? out b fault a (internal signal) fault b (internal signal) normal operation out b shorted to v cc t del fault cleared stby (*) normal operation out b shorted to gnd t del fault cleared normal operation device latched device latched device unlatched
application information vnh2sp30-e 22/33 be inserted to limit the current sunk from the microcontroller i/os. if i rmax is the maximum target reverse current through c i/os, the series resistor is: figure 34. half-bridge configuration note: the vnh2sp30-e can be used as a high power half-bridge driver achieving an on resistance per leg of 9.5m . figure 35. multi-motors configuration note: the vnh2sp30-e can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. diag x /en x pins allow to put unused half-bridges in high impedance. m out a out a out b out b v cc pwm diag a /en a in a diag b /en b in b gnd b gnd a gnd b gnd a pwm diag a /en a in a diag b /en b in b m 2 out a out a out b out b v cc pwm diag a /en a in a diag b /en b in b gnd b gnd a gnd b gnd a pwm diag a /en a in a diag b /en b in b m 1 m 3
vnh2sp30-e application information 23/33 figure 36. waveforms in full bridge operation normal operation (diag a /en a =1, diag b /en b =1) in a in b pwm out a out b i outa -> outb diag a /en a diag b /en b diag b /en b in a in b pwm out a out b diag a /en a normal operation (diag a /en a =1, diag b /en b = 0 and diag a /en a =0, diag b /en b =1) normal operation out a shorted to ground normal operation in a in b t j diag a /en a diag b /en b i lim t tsd t tr t j > t tr current limitation/thermal shutdown or out a shorted to ground cs (*) cs cs i outa -> outb i outa -> outb t del t del load connected between out a , out b load connected between out a , out b (*) cs behavior during pwm mode will depend on pwm frequency and duty cycle.
application information vnh2sp30-e 24/33 figure 37. waveforms in full bridge operation (continued) normal operation out a shorted to v cc normal operation undervoltage shutdown in a in b out a out b diag b /en b diag a /en a out a shorted to v cc and undervoltage shutdown cs v < nominal i outa -> outb undefined undefined
vnh2sp30-e package and pcb thermal data 25/33 4 package and pcb thermal data 4.1 powersso-30 thermal data figure 38. multipowerso-30? pc board note: layout condition of r th and z th measurements (pcb fr4 area = 58mm x 58mm, pcb thickness = 2mm. cu thickness = 35 m, copper areas: from minimum pad layout to 16cm 2 ). figure 39. chipset configuration figure 40. auto and mutual r thj-amb vs pcb copper area in open box free air condition high side chip hs ab low side chip a low side chip b ls a ls b 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 cm 2 of cu area (refer to pcb layout) c/w rthhs rthls rthhsls rthlsls
package and pcb thermal data vnh2sp30-e 26/33 4.1.1 thermal calculation in clockwis e and anti-clockwise operation in steady-state mode 4.1.2 thermal resistances definition (v alues according to the pcb heatsink area) r thhs = r thhsa = r thhsb = high side chip thermal resistance junction to ambient (hs a or hs b in on state) r thls = r thlsa = r thlsb = low side chip thermal resistance junction to ambient r thhsls = r thhsalsb = r thhsblsa = mutual thermal resistance junction to ambient between high side and low side chips r thlsls = r thlsalsb = mutual thermal resistance junction to ambient between low side chips 4.1.3 thermal calculation in transient mode (a) t jhsab = z thhs x p dhsab + z thhsls x (p dlsa + p dlsb ) + t amb t jlsa = z thhsls x p dhsab + z thls x p dlsa + z thlsls x p dlsb + t amb t jlsb = z thhsls x p dhsab + z thlsls x p dlsa + z thls x p dlsb + t amb 4.1.4 single pulse ther mal impedance definition (values according to the pcb heatsink area) z thhs = high side chip thermal impedance junction to ambient z thls = z thlsa = z thlsb = low side chip thermal impedance junction to ambient z thhsls = z thhsablsa = z thhsablsb = mutual thermal impedance junction to ambient between high side and low side chips z thlsls = z thlsalsb = mutual thermal impedance junction to ambient between low side chips table 15. thermal calculation in clockwise and anti-clockwise operation in steady- state mode hs a hs b ls a ls b t jhsab t jlsa t jlsb on off off on p dhsa x r thhs + p dlsb x r thhsls + t amb p dhsa x r thhsls + p dlsb x r thlsls + t amb p dhsa x r thhsls + p dlsb x r thls + t amb off on on off p dhsb x r thhs + p dlsa x r thhsls + t amb p dhsb x r thhsls + p dlsa x r thls + t amb p dhsb x r thhsls + p dlsa x r thlsls + t amb a. calculation is valid in an y dynamic operating condition. p d values set by user.
vnh2sp30-e package and pcb thermal data 27/33 equation 1: pulse calculation formula figure 41. multipowerso-30 hsd thermal impedance junction ambient single pulse figure 42. multipowerso-30 lsd thermal impedance junction ambient single pulse z th r th z thtp 1 ? () + t = where t p t ? = 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 tim e (sec) c/w 16 cm2 footprint 8 cm2 4 cm2 16 cm2 footprint 8 cm2 4 cm2 zthhs zthhsls 0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000 tim e (sec) c/w 16 cm2 footprint 8 cm2 4 cm2 16 cm2 footprint 8 cm2 4 cm2 zthls zthlsls
package and pcb thermal data vnh2sp30-e 28/33 figure 43. thermal fitting model of an h-bridge in multipowerso-30 table 16. thermal parameters (1) 1. the blank space means that the val ue is the same as the previous one. area/island (cm 2 )footprint4 8 16 r1 = r7 (c/w) 0.05 r2 = r8 (c/w) 0.3 r3 (c/w) 0.5 r4 (c/w) 1.3 r5 (c/w) 14 r6 (c/w) 44.7 39.1 31.6 23.7 r9 = r15 (c/w) 0.2 r10 = r16 (c/w) 0.4 r11 = r17 (c/w) 0.8 r12 = r18 (c/w) 1.5 r13 = r19 (c/w) 20 r14 = r20 (c/w) 46.9 36.1 30.4 20.8 r21 = r22 = r23 (c/w) 115 c1 = c7 (w.s/c) 0.005 c2 = c8 (w.s/c) 0.008 c3 = c11 = c17 (w.s/c) 0.01 c4 = c13 = c19 (w.s/c) 0.3 c5 (w.s/c) 0.6 c6 (w.s/c) 5 7 9 11 c9 = c15 (w.s/c) 0.003 c10 = c16 (w.s/c) 0.006 c12 = c18 (w.s/c) 0.075 c14 = c20 (w.s/c) 2.5 3.5 4.5 5.5
vnh2sp30-e package and packing information 29/33 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in ecopack ? packages. ecopack ? packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at www.st.com. 5.2 multipowerso-30 package mechanical data figure 44. multipowerso-30 package outline
package and packing information vnh2sp30-e 30/33 figure 45. multipowerso-30 suggested pad layout table 17. multipowerso-30 mechanical data symbol millimeters min typ max a 2.35 a2 1.85 2.25 a3 0 0.1 b 0.42 0.58 c 0.23 0.32 d 17.1 17.2 17.3 e 18.85 19.15 e1 15.9 16 16.1 e1 f1 5.55 6.05 f2 4.6 5.1 f3 9.6 10.1 l 0.8 1.15 n 10deg s 0deg 7deg
vnh2sp30-e package and packing information 31/33 5.3 packing information note: the devices can be packed in tube or tape and reel shipments (see the device summary on page 1 for packaging quantities). figure 46. multipowerso-30 tube shipment (no suffix) figure 47. multipowerso-30 tape and reel shipment (suffix ?tr?) a b c dimension mm base q.ty 29 bulk q.ty 435 tube length ( 0.5) 532 a3.82 b23.6 c ( 0.13) 0.8 reel dimensions so-28 tube shipment (no suffix) dimension mm base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 d (min) 20.2 g (+ 2 / -0) 32 n (min) 100 t (max) 38.4 to p cover tape start no components no components components 500 mm min 500 mm min empty components pockets user direction of feed tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 description dimension mm tape width w 32 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 2 hole position f ( 0.1) 14.2 compartment depth k (max) 2.2 end
revision history vnh2sp30-e 32/33 6 revision history table 18. document revision history date revision description of changes sep-2004 1 first issue dec- 2004 2 inserted t off(min) test condition modification and note modified i rm figure number feb-2005 3 minor changes apr-2005 4 public release 01-sep-2006 5 document converted into new st corporate template. added table of contents, list of tables and list of figures removed figure number from package outline on page 1 changed features on page 1 to add ecopack ? package added section 1: block diagram and pin description on page 5 added section 2.2: electrical characteristics on page 9 added ?low? and ?high? to parameters for i inl and i inh in ta b l e 7 o n page 9 inserted note in figure 32 on page 20 added vertical limitation line to left side arrow of t d(off) to figure 7 on page 13 added section 4.1: powersso-30 thermal data on page 25 added section 5: package and packing information on page 29 added section 5.3: packing information on page 31 updated disclaimer (last page) to include a mention about the use of st products in automotive applications 15-may-2007 6 document reformatted and converted into new st template. 06-feb-2008 7 corrected heat slug numbers in table 3: pin definitions and functions . 02-oct-2008 8 added new infomation in table 6: power section added figure 33: behavior in fault condition (how a fault can be cleared)
vnh2sp30-e 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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